The Era of Large-Format Photomasks: Scaling the Reticle Limit for the AI Compute Age

The semiconductor industry is rapidly approaching a fundamental physical bottleneck: the reticle size limit. As the demand for high-performance computing (HPC) and artificial intelligence (AI) chips grows, chip designers are increasingly pushed toward multi-die architectures, such as chiplets and advanced 3D packaging, to circumvent the limitations of traditional 26mm x 33mm photomask formats. The industry's transition from aspiration to a formalized roadmap for large-format masks represents a pivotal shift in lithography strategy, necessitated by the pursuit of monolithic system-on-chip (SoC) performance and superior energy efficiency. From an industry impact perspective, the adoption of large-format masks is not merely a scaling exercise; it is an economic and technical overhaul of the entire backend and manufacturing pipeline. By expanding the printable area, designers can integrate significantly more compute, memory, and I/O into a single package without the yield degradation and thermal resistance penalties associated with complex interposer-based packaging. However, this shift mandates a synchronized evolution across the entire supply chain. Photomask manufacturers must invest in new inspection and repair tools capable of handling larger surface areas, while scanner original equipment manufacturers (OEMs) must re-engineer optical systems to maintain critical dimension (CD) uniformity across an expanded field. The supply chain implications are profound. Because current mask-making infrastructure is optimized for standard field sizes, the move to larger formats will require substantial capital expenditure (CapEx) from merchant mask shops and captive fabs. This creates a barrier to entry that may consolidate the photomask market further. Furthermore, the ecosystem must standardize these larger formats early to ensure cross-vendor interoperability. If the industry fails to align on a universal large-format standard, we risk a fragmented landscape where proprietary lithography solutions hamper the democratization of advanced chip design. Looking toward the future, the successful implementation of large-format masks will likely redefine the boundaries of what is possible in monolithic integration. As we push toward the 2nm node and beyond, this transition will be the cornerstone of sustaining the performance gains required by the next decade of generative AI and exascale computing workloads.